Switching power supplies utilize a plurality of switches which are turned on and off to switch an input DC voltage at a first level across a transformer to a load, the output voltage disposed at a different and lower DC voltage level than the input DC voltage. For some power supply applications, the initial input DC voltage may be at a high level of, for example, 75 volts. This voltage then must be reduced to a fairly low voltage, on the order of less than 3 volts, with future voltages going as low as 1 volt. Large differences between input and output voltage levels will result in very short pulse width switching pulses that switch the transistors in the switching power supply relative to the overall period of the switching operation. Since jitter or ripple on the output voltage is a function of how well the pulse width is controlled, it is important that the resolution of the falling edge of the pulse, i.e., the edge that defines the width of the pulse, be tightly controlled. This resolution is defined as a percentage of the entire pulse width. Typically, the pulse width is generated with some type of counter that requires a time base which is utilized to define the trailing edge of the pulse. In order to maintain very low ripple, a very tightly controlled pulse width will be required. This can result in the requirement for a fairly high clock frequency that is output by a clock generator. For example, if a resolution of approximately 40 nanoseconds is required for the definition of the pulse width, then a 24 MHz clock would suffice. This will allow the falling edge of a pulse to be defined within +/−40 nanoseconds. However, for a power supply that steps down from 75 volts to 3 volts or even 1 volt, this would result in a considerable amount of ripple. To increase the resolution, it may be that a resolution on the order of 1 nanosecond is required. This will require a clock up in the 1 GHz range. The problem with such clocks is they tend to be complex, as they must be accurate clocks, and they also draw considerable power. Thus, it would be desirable to have less complexity associated with a lower speed clock, but gain the resolution of a higher speed clock.